- LPU MCA Semester 1
- CAP366
- Unit 7
CAP366 · Unit 7: Memory management
Logical and physical address space, address binding
10 practice questions · in the ETE syllabus
Key points
- Logical address from CPU, physical address seen by memory
- Binding at compile, load or execution time
- Only execution-time binding makes logical and physical differ
- Physical = base + logical, after limit check
A logical (virtual) address is generated by the CPU; a physical address is the one seen by the memory unit. The set of all logical addresses is the logical address space and the set of corresponding physical addresses is the physical address space. The memory-management unit (MMU) maps one to the other at run time.
Address binding can happen at three times:
| Binding time | Needs | Logical vs physical |
|---|---|---|
| Compile time | Memory location known in advance; recompile to move | Same |
| Load time | Relocatable code; reload to move | Same |
| Execution time | Hardware support such as a relocation register | Different |
In the simple scheme the MMU adds the relocation (base) register to every logical address after checking it against the limit register. With base 14000, logical address 346 maps to physical address 14346. If a logical address is not below the limit, the hardware traps to the operating system.
Execution-time binding lets the OS move a process, for example during compaction, by only changing the base register.
Exam trap: the limit check comes before the base is added, and an address equal to the limit is already illegal because valid addresses run from 0 to limit - 1.
Try two questions
A relocation register holds 14000. What physical address does the logical address 346 map to?
- 346
- 14346
- 13654
- 14000
Show the answer
B. The MMU adds the relocation register to the logical address: 14000 + 346 = 14346.
Why not A: That is the logical address itself, ignoring the base.
Why not C: Subtracting the logical address from the base is not how relocation works.
Why not D: That is the base alone, with no offset.
A process has relocation base 40000 and limit 5000. It issues the logical addresses 4999, 5000, 120, 7500 and 0 in turn. How many of these cause an addressing trap?
- 1
- 3
- 4
- 2
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D. Legal logical addresses run from 0 to 4999. The addresses 5000 and 7500 are outside, so two trap.
Why not A: Both 5000 and 7500 exceed the legal range, so one is not enough.
Why not B: Only addresses at or above the limit trap; 4999, 120 and 0 are legal.
Why not C: Only two of the five addresses are outside the range.